The invention refers to a data bus with several components.
Such data buses are becoming increasingly wide spread in use. In buildings, for example, they serve to interconnect the different electrical switches, energy consuming devices and such other similar devices of a building, and to transmit control commands among the components. Further applications include networking of machine control systems in an industrial environment, (for example, a production line, data buses in airplanes for the various actuation and control components), as well as in land vehicles having corresponding devices for switching, transforming and consuming electrical energy.
Two different designs of data buses exist. One design concerns the synchronized model in which the bus master emits a synchronizing pulse with a predetermined elementary frequency. In the time span between two different timing pulses, the components access the data bus within a defined time frame. The point in time of their respective transmission authorization is, as a rule, determined by their transmission priority, and every component transmits in a defined time frame after the output of the synchronizing pulse.
Such a data bus possesses the advantage of being able to function without data collisions among the different components, since every component has a defined time frame available for its data transmission. On the other hand, such a data bus is relatively slow because the cycle time is determined by the number of the components; hence, a great number of components results in a lowering of the fundamental frequency. In addition, there is the difficulty of supplying with one and the same data bus concept not only a defined number of components, but rather a number of components that deviates from the defined number. Thus time frames are also made available for the maximum number of components which can be integrated into the data bus, which results in a reduction of the corresponding cycle time.
The second data bus concept is known as an asynchronous data bus. Here the components transmit their data in the order of their respective, hierarchy-dependent transmission authorization. As a result, the component with the highest priority rank can transmit to the data bus at all times, which has the disadvantage that this component can jam the data bus, i.e., it becomes impossible to transmit data for those components that rank lower in the priority-dependent transmission hierarchy. In addition, the problem exists that components may collide, because depending on the signal run times several components may want to access the seemingly free data bus simultaneously, and they are informed of the transmission of another component only while they are already transmitting their own signal. This possibility requires costly collision prevention strategies, such as CSMA/CD.
The invention is based on the task to create a data bus of the type mentioned in the introduction, which combines the advantages of a synchronous and an asynchronous data bus.
The invention solves this task via the characteristics of Patent claim 1.
The data bus, which conforms to the definition of the invention, possesses characteristics of both a synchronous and an asynchronous data bus. The synchronizing pulse is an unequivocal characteristic of a synchronous data bus. The declared cycle time is found neither on an asynchronous nor on a synchronous data bus. The cycle""s time span is located between the transmission time span of the component with the highest priority ranking and the cumulative transmission time of all components. On a data bus with 100 components, this time span is chosen so that for example the 50 components with the highest priority all may transmit to the data bus during one cycle time, while in this case the lower ranked components cannot gain access to the data bus.
The number 50, i.e., approximately half of the maximum number of components, is to be understood merely as a point of reference. This number may range from 2 to 95 components in a given application. Crucial is only that the cycle time is indeed significantly smaller than the cumulative transmission time of all components. Therefore, it is never possible that all components can transmit to the data bus in one cycle. On the other hand, this eliminates the aforementioned problem of providing time frames for possibly non-existent bus components, and a cycle time is obtained which fulfills the respective requirements.
By allocating a hierarchical transmission authorization order, the collision prevention algorithms, which are typical for an asynchronous data bus, become superfluous. At the same time, by choosing the transmission time, as described, it is assured that among components that follow in the transmission hierarchy, in case the previous component does not transmit, only those components access the data bus which are actually transmitting, and the components which do not use the data bus for their transmission during the cycle are taken into consideration only insofar as it is confirmed that they are indeed not transmitting. This is achieved by taking into consideration the signal run times on the data bus.
The basic principle behind the invention can be described as follows:
In theory, every component receives the chance to transmit data to the data bus. However, in actuality its ability to transmit data is subject to a hierarchical order. The later a component is designated to transmit within a given cycle, the lower is its ranking in the transmission hierarchy. If the time of its transmission lies after the completion of the cycle, then it may transmit at the earliest in the next cycle. If at that point a corresponding number of components with a higher ranking are once more transmitting, then this particular component cannot even send at this point in time, etc. Its ability to transmit thus depends in every transmission cycle on how many other, higher ranking components are transmitting.
The cycle time is determined depending on how many components must have the option to transmit in every cycle. The cycle time is adjusted for the number of these privileged components. Whether the other components do get the chance to transmit during a cycle depends entirely on how many of the privileged components indeed do (not) transmit, and on how many other components are transmitting which have a higher priority rank.
During a component""s transmission, it may happen that the component""s transmission is being completed at the same time as the transmission of the synchronizing pulse takes place, i.e., that it coincides with the end of the cycle, or even takes place after it. For this situation, different solutions may be used within the framework of the invention. One solution consists of delaying the synchronizing pulse until the component has completed its transmission.
In order to be able to maintain the elementary frequency despite this occurrence, the following synchronizing pulse is calculated, in terms of its output time, in such a way that it is synchronized with the next to last previous synchronizing pulse. If one designates the next to last previous synchronizing pulse as the first pulse and the following ones as pulses number two, three, etc., then the interval between the first and the second pulse is longer than the cycle time, while the phase between the second and the third pulse is shorter than the cycle time. If once more a component is transmitting to the data bus at the time of the output of the third synchronizing pulse, then the third synchronizing pulse is also emitted with a delay. The following synchronizing pulse, i.e., in this case the fourth one, compensates for the time overrun.
An alternative solution provides that the component does not transmit if the end of its transmission coincides with the end of the cycle, or if its transmission would end after the end of the cycle. This solution has the advantage of an always constant cycle time. Therefore adjustments, such as those described in the first alternative, are not necessary.